Spatial bandgap modifications and energy shift of semiconductor structures

ABSTRACT

Semiconductor substrate is disclosed having quantum wells having first bandgap, and quantum wells having second bandgap greater than first bandgap. Semiconductor structure is disclosed comprising substrate having quantum wells having given bandgap, other quantum wells modified to bandgap greater than given bandgap. Semiconductor substrate is disclosed comprising wafer having quantum wells, section of first bandgap, and section of second bandgap greater than first bandgap. Method for forming semiconductor substrate is provided, comprising providing wafer having given bandgap, depositing dielectric cap on portion and rapid thermal annealing to tuned bandgap greater than given bandgap. Semiconductor structure is disclosed comprising substrate having quantum wells modified by depositing cap and rapid thermal annealing to tuned bandgap greater than given bandgap. Method for forming semiconductor substrate is disclosed, comprising providing wafer having quantum wells having given bandgap, depositing cap on portion and rapid thermal annealing to tuned bandgap greater than given bandgap.

REFERENCE TO PENDING PRIOR PATENT APPLICATION

This patent application claims benefit of pending prior U.S. ProvisionalPatent Application Ser. No. 60/462,888, filed Apr. 15, 03 by PeidongWang et al. for SPATIAL BANDGAP MODIFICATIONS AND ENERGY SHIFT OFSEMICONDUCTOR STRUCTURES (Attorney's Docket No. AHURA-10 PROV), whichpatent application is hereby incorporated herein by reference.

FIELD OF THE INVENTION

This invention relates to optical components in general, and moreparticularly to optical components for generating light.

BACKGROUND OF THE INVENTION

In many applications it may be necessary and/or desirable to generatelight.

Different optical components are well known in the art for generatinglight. By way of example but not limitation, semiconductor lasers, suchas vertical cavity surface emitting lasers (VCSEL's), are well known inthe art for generating light. Depending on the particular constructionused, the light source may emit light across different portions of thewavelength spectrum. By way of example, many semiconductor-based lightsources emit light across a relatively narrow portion of the wavelengthspectrum. However, in many applications it may be necessary and/ordesirable to provide a semiconductor light source which emits lightacross a relatively broad band of wavelengths.

The present invention is directed to a novel semiconductor light sourcefor emitting light across an extended optical bandwidth.

SUMMARY OF THE INVENTION

An object of the invention is to provide a monolithically integratedsemiconductor device having discrete sections of quantum wells with adifferent bandgap at each section.

Another object of the invention is to provide a monolithicallyintegrated semiconductor device having discrete sections of quantumwells with a different bandgap at each section and means to individuallyexcite each section so as to tune the spectral output from thesemiconductor device.

A further object of the invention is to provide a monolithicallyintegrated semiconductor device having discrete sections of quantumwells with a different bandgap shift at each section and multiple lasersources formed by each of the sections, respectively.

A still further object of the invention is to provide a method forforming a monolithically integrated semiconductor substrate havingdiscrete sections of quantum wells with a different bandgap shift ateach section.

With the above and other objects in view, as will hereinafter appear,there is provided a semiconductor substrate having a given horizontalcross-section, a first region defined in a first portion of the givenhorizontal cross-section of the substrate, and a second region definedin a second portion of the given horizontal cross-section of thesubstrate, the second region adjacent to and integral with the firstregion, a first given plurality of quantum wells formed in the firstregion, the first given plurality of quantum wells having a first givenbandgap, and a second given plurality of quantum wells formed in thesecond region, the second given plurality of quantum wells having asecond given bandgap, wherein the first given bandgap is less than thesecond given bandgap.

In accordance with a further feature of the invention, there is provideda semiconductor structure comprising:

a semiconductor substrate having a given horizontal cross-section, afirst section defined in one portion of the given horizontalcross-section of the substrate, and a second section defined in anotherportion of the given horizontal cross-section of the substrate;

a first plurality of quantum wells formed in the first section, thefirst plurality of quantum wells having a given bandgap;

a second plurality of quantum wells formed in the second section, thesecond plurality of quantum wells modified by depositing a dielectriccap on the second section, and rapid thermal annealing of the dielectriccap for a given time and at a given temperature, so as to tune thesecond plurality of quantum wells to a tuned bandgap;

wherein the tuned bandgap is greater than the given bandgap.

In accordance with a further feature of the invention, there is provideda semiconductor substrate comprising:

a single semiconductor wafer having a first end and a second end inopposition to one another, and a longitudinal axis formed between thefirst end and the second end;

a plurality of quantum wells formed in the single semiconductor waferbetween the first end and the second end, a first section of theplurality of quantum wells having a first given bandgap, and a secondsection of the plurality of quantum wells having a second given bandgap;

wherein the second given bandgap is greater than the first givenbandgap.

In accordance with a still further feature of the invention, there isprovided a method for forming a semiconductor substrate, the methodcomprising:

providing a single semiconductor wafer having a first end and a secondend in opposition to one another, a longitudinal axis formed between thefirst end and the second end, a top surface and a bottom surface inopposition to one another, a plurality of quantum wells disposed in thesemiconductor wafer, and the plurality of quantum wells having a givenbandgap;

depositing a first dielectric cap on a first given portion of the topsurface of the single semiconductor wafer; and

rapid thermal annealing of the first dielectric cap deposited on the topsurface of the single semiconductor wafer to tune the plurality ofquantum wells disposed beneath the first dielectric cap from the givenbandgap to a first tuned bandgap;

wherein the first tuned bandgap is greater than the given bandgap.

In accordance with a still further feature of the invention, there isprovided an semiconductor structure comprising:

a semiconductor substrate having a given horizontal cross-section, afirst section defined in one portion of the given horizontalcross-section of the substrate, and a second section defined in anotherportion of the given horizontal cross-section of the substrate;

a first plurality of quantum wells formed in the first section, thefirst plurality of quantum wells having a given bandgap;

a second plurality of quantum wells formed in the second section, thesecond plurality of quantum wells modified by depositing a cap on thesecond section, and rapid thermal annealing of the cap for a given timeand at a given temperature, so as to tune the second plurality ofquantum wells to a tuned bandgap;

wherein the tuned bandgap is greater than the given bandgap.

In accordance with a still further feature of the invention, there isprovided a method for forming a semiconductor substrate, the methodcomprising:

providing a single semiconductor wafer having a first end and a secondend in opposition to one another, a longitudinal axis formed between thefirst end and the second end, a top surface and a bottom surface inopposition to one another, a plurality of quantum wells disposed in thesemiconductor wafer, and the plurality of quantum wells having a givenbandgap;

depositing a first cap on a first given portion of the top surface ofthe single semiconductor wafer; and

rapid thermal annealing of the first cap deposited on the top surface ofthe single semiconductor material to tune the plurality of quantum wellsdisposed beneath the first cap from the given bandgap to a first tunedbandgap;

wherein the first tuned bandgap is greater than the given bandgap.

The above and other features of the invention, including various noveldetails of construction and combinations of parts and method steps, willnow be more particularly described with reference to the accompanyingdrawings and pointed out in the claims. It will be understood that theparticular devices and method steps embodying the invention are shown byway of illustration only and not as limitations of the invention. Theprinciples and features of this invention may be employed in various andnumerous embodiments without departing from the scope of the invention.

BRIEF DESCRIPTION OF THE DRAWINGS

These and other objects and features of the present invention will bemore fully disclosed or rendered obvious by the following detaileddescription of the preferred embodiments of the invention, which are tobe considered together with the accompanying drawings wherein likenumbers refer to like parts, and further wherein:

FIGS. 1A-1J are schematic diagrams of a preferred embodiment of thenovel bandgap modification process of the present invention in whichthere is shown a set of iterative steps including rapid thermalannealing to form a silicon wafer having four discrete sections ofquantum wells with a different bandgap shift at each section;

FIG. 2 is a graphical diagram in which there is shown the bandgap tuningand photoluminescence shift for each of the sections of the siliconwater shown in FIGS. 1A-1J;

FIGS. 3A-3C are schematic diagrams of a preferred embodiment of thenovel bandgap modification process of the present invention in whichthere is shown a set of steps for adjusting the spatial bandgap shift ofthe silicon wafer by providing a stepped sacrificial layer between thesilicon wafer and the dielectric cap;

FIG. 4 is a schematic diagram of a preferred embodiment of the novelbandgap modification process of the present invention in which there isshown a graded sacrificial layer between the silicon wafer and thedielectric cap in place of the stepped sacrificial layer as shown inFIGS. 3A-3C;

FIGS. 5A-5C are schematic diagrams of a preferred embodiment of thenovel bandgap modification process of the present invention in which ionimplantation together with an implantation mask is used to supplementthe rapid thermal annealing of the silicon wafer as shown in FIGS.1A-1J, 2, 3A-3C and 4;

FIG. 6 is a graphical diagram in which there is shown photoluminescenceshifts of 130 nm in laser emission, where the photoluminescent shiftsare created by the impurity free vacancy disordering (IFVD) technique ofFIG. 1;

FIG. 7 is a graphical diagram in which there is shown an amplifiedspontaneous emission spectrum based on a silicon wafer formed with threeimpurity free vacancy disordered (IFVD) sections using the novel bandgapmodification process of the present invention, such that the output ofthe light sources is broadened to a full-width half-maximum (FWHM) of 90nm (as opposed to a conventional broadened output having a FWHM of 25nm); and

FIG. 8 is a schematic diagram of a semiconductor device formed inaccordance with the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The present invention involves a modification of bandgap structures andenergy shift of semiconductor materials spatially (in a linear dimensionor two dimensions) through masking, potential implantation, andsubsequent thermal processes. Semiconductor intermixing is used to causebandgap shifting. By varying the bandgap energy at multiple sections ofa single wafer through this process, a variety of semiconductor devicescan be monolithically integrated on a single wafer.

Looking first at FIGS. 1A-1J, there is shown one preferred embodiment ofthe present invention. More particularly, in FIGS. 1A-1J there is showna series of steps to tune quantum wells within a single semiconductorwafer 5 so as to form an implantation free semiconductor wafer 10 (FIG.1J) having four sections 15A, 15B, 15C, 15D of quantum wells withdiffering bandgaps at each of sections 15A, 15B, 15C, 15D, respectively.This process involves deposition of a dielectric cap 20, such as SiO₂,TiO₂, Si₃N₄, Ta₂O₅, or a B. P doped glass, on semiconductor wafer 5(comprising the quantum wells to be tuned) through electron beamsputtering (e-beam) or ion beam sputtering (ion-beam). SiO2 dielectriccap 20 is patterned selectively through photolithography using aphotoresist 23 so as to form an uncapped region 25A and a capped region25B (FIGS. 1C-1E).

Semiconductor wafer 5 is next subjected to rapid thermal annealing (RTA)at a specified time and a specified temperature so as to tune thebandgap of the quantum wells beneath capped region 25B (FIG. 1E).Preferably, the specified temperature is between about 600° C. and about900° C. Alternatively, the specified temperature is above 900° C. Anuncapped region 25A of semiconductor 5 has less surface modificationsthan capped region 25B of semiconductor 5 and hence uncapped region 25Ahas less bandgap tuning. This process is preferably iterated severaltimes with smaller capped regions 25C and 25D (FIGS. 1F, 1G, 1H, and 1I)so as to achieve sections 15A, 15B, 15C, 15D, each having differentbandgap tuning. Inasmuch as there is demonstrated a four sectionprocess, the same process can be extended to more than four sections.

Referring now to FIG. 2, there is shown a graph of a photoluminescenceshift 30A, 30B, 30C, 30D induced at each of the four sections 15A, 15B,15C, 15D through the bandgap tuning of the present invention.

In another preferred embodiment of the present invention (not shown), animplantation free semiconductor wafer is formed using a reverse processof the previous technique. More particularly, with this form of theinvention, locally different patterns of dielectric films that shift thebandgap upon rapid thermal annealing (RTA) are progressively lifted offafter each step of rapid thermal annealing (RTA), whereby to provide thevarious sections of distinct bandgap shifting.

Referring now to FIGS. 3A-3C there is shown another preferred embodimentof the present invention. More particularly, in FIGS. 3A-3C, there isshown a novel bandgap modification process in which the spatial bandgapshift of semiconductor 5 (comprising the quantum wells to bebandgap-shifted)is adjusted for sections 15A, 15B, 15C, 15D bydesigning, depositing, or etching a sacrificial layer 35, using an etchstop 36, so as to properly configure dielectric cap 20. Theconfiguration of sacrificial layer 35 is preferably stepped (FIGS. 3Aand 3B) or so as to yield discrete bandgap-shifted sections 15A, 15B,15C, 15D (FIG. 3C). However, other configurations may be used.Sacrificial layer 35 includes one or more semiconductor, dielectric, ormetal layers. By varying the thickness of sacrificial layer 35 above thequantum wells, different bandgap shifts will occur in each of sections15A, 15B, 15C, 15D, respectively, after the step of rapid thermalannealing (RTA). Semiconductor wafer 5 can further be processed afterremoving these sacrificial layers 35.

Referring now to FIG. 4, there is shown another preferred embodiment ofthe present invention. More particularly, in FIG. 4, smooth or gradedsacrificial top cladding layers 35 are deposited above etch stop 36 toappropriately pattern dielectric cap 20. Sacrificial top cladding layers35 are created using one or more techniques. These techniques include,but are not limited to, gray scale masking and dry etching techniques.Another way to achieve graded sacrificial top cladding 35 is to patternvariable widths of photoresist along the waveguide. The photoresists arethen reflowed in an oven to form the desired thickness gradient. Usingdry etching, the thickness gradient is transferred to sacrificial topcladding layers 35. Dielectric cap 20 is then deposited on sacrificialtop cladding layer 35 for the step of the rapid thermal annealing (RTA)process. The other portions of the process may be the same as describedhereinabove.

Referring now to FIGS. 5A-5C, there is shown another preferredembodiment of the present invention. More particularly, in FIGS. 5A-5C,there is shown an implantation mask 40 (FIG. 5A) used together withimplantation flux 45 (FIG. 5B) to provide ion-implantation to supplementthe bandgap shift provided by the rapid thermal annealing processesdescribed hereinabove. For example, ion implantation is preferably usedto introduce impurities or vacancies at varying heights in thesemiconductor (comprising the quantum wells to be bandgap shifted) andthus after rapid thermal annealing (RTA), different amounts of bandgapshift occur at different locations. Ion implantation enhancesdisordering and bandgap shift, hence, it may also be used in place ofdielectric material 20 as the instigator of disordering. The closer theimplantation center of gravity is to the target quantum wells, the morethat section is bound to disorder under rapid thermal annealing (RTA).Thus, by having different thicknesses of implantation mask 40, aspatially varying disordering and bandgap shift is produced.

Still referring to FIGS. 5A-5C, if the thickness of implantation mask 40is chosen properly, some of implantation damage 50 may occur in mask 40so as to reduce the total damage in semiconductor wafer 5.

In addition to the distance of the implantation effective center fromthe active region, the dosage of implantation flux 45 also affects theamount of disordering. Thus, by varying the dosage of implantation flux45 across sections 15A, 15B, 15C, 15D of wafer 5, spatial disordering isprovided.

Referring now to FIG. 6, there is shown laser wavelength emissions 55formed by impurity free vacancy disordering (IFVD) demonstrating abandgap tuning of 130 nm of emission wavelengths using the presentinvention.

Referring now to FIG. 7, there is shown an amplified spontaneousemission spectrum 60 based on 3 impurity free vacancy disordering (IFVD)sections so as to effect the broadening of light sources 65, 70, 75 tofull-width half-maximum (FWHM) of 90 nm as opposed to a conventionalbroadened output having a FWHM of 25 nm.

Looking next at FIG. 8, there is shown a laser 105 formed in accordancewith the present invention. Laser 105 comprises a waveguide 110 with aplurality of distinct gain sections 112, a front mirror 115 and a rearmirror 117. The laser 105 is configured so that each of the distinctgain sections 112 can be individually excited so as to permit the outputwavelength(s) of the laser to be controlled. Further details regardinglaser 105 are disclosed in pending U.S. patent application Ser. No.10/800,206, filed Mar. 12, 04 by Daryoosh Vakhshoori et al. for EXTENDEDOPTICAL BANDWIDTH SEMICONDUCTOR SOURCE (Attorney's Docket No. AHURA-5),which patent application is hereby incorporated herein by reference. Inaccordance with the present invention, distinct gain sections 112 may becreated by disordering-induced bandgap shifting of the quantum wells soas to provide the desired bandgap tuning and resulting photoluminescentshifts.

In the foregoing discussion of the invention, the desired bandgap shiftis discussed in the context of placing a dielectric material above thequantum wells and then rapid thermal annealing (RTA) so as to induce thedesired disordering and hence achieve the intended bandgap shift.However, it should also be appreciated that the invention can bepracticed by substituting appropriate non-dielectric materials, such assemiconductors and metals, in place of the dielectric material.

1. A semiconductor substrate having a given horizontal cross-section, afirst region defined in a first portion of the given horizontalcross-section of the substrate, and a second region defined in a secondportion of the given horizontal cross-section of the substrate, thesecond region adjacent to and integral with the first region, a firstgiven plurality of quantum wells formed in the first region, the firstgiven plurality of quantum wells having a first given bandgap, and asecond given plurality of quantum wells formed in the second region, thesecond given plurality of quantum wells having a second given bandgap,wherein the first given bandgap is less than the second given bandgap.2. A semiconductor substrate according to claim 1 further comprising athird region defined in a third portion of the given horizontalcross-section of the substrate, the third region adjacent to andintegral with the second region, a third given plurality of quantumwells formed in the third region, and the third given plurality ofquantum wells having a third given bandgap, wherein the third givenbandgap is less than the second given bandgap.
 3. A semiconductorstructure comprising: a semiconductor substrate having a givenhorizontal cross-section, a first section defined in one portion of thegiven horizontal cross-section of the substrate, and a second sectiondefined in another portion of the given horizontal cross-section of thesubstrate; a first plurality of quantum wells formed in the firstsection, the first plurality of quantum wells having a given bandgap; asecond plurality of quantum wells formed in the second section, thesecond plurality of quantum wells modified by depositing a dielectriccap on the second section, and rapid thermal annealing of the dielectriccap for a given time and at a given temperature, so as to tune thesecond plurality of quantum wells to a tuned bandgap; wherein the tunedbandgap is greater than the given bandgap.
 4. A semiconductor substrateaccording to claim 3 wherein the dielectric cap comprises SiO₂.
 5. Asemiconductor substrate according to claim 3 wherein the dielectric capcomprises TiO₂.
 6. A semiconductor substrate according to claim 3wherein the dielectric cap comprises Si₃N₄.
 7. A semiconductor substrateaccording to claim 3 wherein the dielectric cap comprises Ta₂O₅.
 8. Asemiconductor substrate according to claim 3 wherein the dielectric capcomprises B, P doped glass.
 9. A semiconductor substrate according toclaim 3 wherein the dielectric cap is deposited on the second section byelectron beam sputtering.
 10. A semiconductor substrate according toclaim 3 wherein the dielectric cap is deposited on the second section byion beam sputtering.
 11. A semiconductor substrate according to claim 3wherein the given temperature is above 650° C.
 12. A semiconductorsubstrate according to claim 3 wherein the given temperature comprises arange of about 650° C. to about 900° C.
 13. A semiconductor substrateaccording to claim 3 wherein a sacrificial layer is positioned on thesecond section prior to depositing the dielectric cap on the secondsection.
 14. A semiconductor substrate according to claim 13 wherein thesacrificial layer is graded from a first portion at a first height to asecond portion at a second height, and further wherein the first heightis lower than the second height.
 15. A semiconductor substrate accordingto claim 13 wherein the sacrificial layer is stepped from a firstsubstantially flat portion to a second substantially flat portion, andfurther wherein the first substantially flat portion is lower than thesecond substantially flat portion.
 16. A semiconductor substrateaccording to claim 13 wherein the sacrificial layer on the secondsection comprises a given portion of the single semiconductor waferdesignated as the sacrificial layer.
 17. A semiconductor substrateaccording to claim 13 wherein the sacrificial layer positioned on thesecond section comprises a dielectric layer deposited thereon.
 18. Asemiconductor substrate according to claim 13 wherein the sacrificiallayer positioned on the second section comprises a metal layer depositedthereon.
 19. A semiconductor substrate according to claim 3 wherein asacrificial top cladding layer is deposited on the second section priorto depositing a dielectric cap.
 20. A semiconductor substrate accordingto claim 19 wherein the sacrificial top cladding layer comprises astepped top surface.
 21. A semiconductor substrate according to claim 19wherein the sacrificial top cladding layer comprises an inclined topsurface.
 22. A semiconductor substrate according to claim 19 wherein thesacrificial top cladding layer is deposited by a gray scale maskingtechnique.
 23. A semiconductor substrate according to claim 19 whereinthe sacrificial top cladding layer is deposited by a dry etchingtechnique.
 24. A semiconductor substrate according to claim 3 whereinion implantation is provided to the second section.
 25. A semiconductorsubstrate according to claim 24 wherein the ion implantation introducesinto the second section at least one selected from a group consisting ofimpurities and vacancies.
 26. A semiconductor substrate according toclaim 25 wherein the selected at least one of impurities and vacanciesare introduced into the second section at a first given height in afirst area and at a second given height in a second area.
 27. Asemiconductor substrate according to claim 26 wherein an implantationmask is deposited on the top surface of the second section so as tointroduce the at least one of impurities and vacancies at the firstgiven height and the second given height in the first area and thesecond area, respectively.
 28. A semiconductor substrate according toclaim 3 wherein at least one of the first section and the second sectionare individually excited so as to tune output light through thesemiconductor substrate.
 29. A semiconductor substrate according toclaim 3 wherein the semiconductor substrate is a single wafer comprisingmultiple laser sources formed by the first section and the secondsection, respectively.
 30. A semiconductor substrate comprising: asingle semiconductor wafer having a first end and a second end inopposition to one another, and a longitudinal axis formed between thefirst end and the second end; a plurality of quantum wells formed in thesingle semiconductor wafer between the first end and the second end, afirst section of the plurality of quantum wells having a first givenbandgap, and a second section of the plurality of quantum wells having asecond given bandgap; wherein the second given bandgap is greater thanthe first given bandgap.
 31. A semiconductor substrate according toclaim 30 wherein the plurality of quantum wells are configured to havean increasing bandgap shift in a given direction parallel to thelongitudinal axis from the first portion to the second portion.
 32. Asemiconductor substrate according to claim 31 wherein the increasingbandgap shift of the plurality of quantum wells is a substantiallysmooth increase in the given direction parallel to the longitudinalaxis.
 33. A semiconductor substrate according to claim 31 wherein theincreasing bandgap shift of the plurality of quantum wells from thefirst section to the second section comprises at least one given lengthof a substantially constant bandgap shift.
 34. A semiconductor substrateaccording to claim 33 wherein the increasing bandgap shift comprises astepwise increase in the given direction parallel to the longitudinalaxis.
 35. A semiconductor substrate according to claim 33 wherein theplurality of quantum wells are configured in at least two regions, andfurther wherein each of the at least two regions have a substantiallyconstant bandgap in the given direction parallel to the longitudinalaxis, respectively. 36.-46. (canceled)
 47. A method according to claim36 wherein the first dielectric cap deposited on the first given portionhas a first given region and a second given region, the first givenregion having a first given height and the second given area having asecond given height, the first given height being lower than the secondgiven height, wherein the step of rapid thermal annealing of the firstdielectric cap tunes the plurality of quantum cells disposed beneath thefirst given area to a first tuned bandgap and the plurality of quantumwells disposed beneath the second given area to a second tuned bandgap,and wherein the second tuned bandgap is greater than the first tunedbandgap.
 48. A method according to claim 47 wherein the top surface ofthe single semiconductor wafer is entirely covered by the first givenportion.
 49. A method according to claim 47 wherein the top surface ofthe single semiconductor wafer is partially covered by the first givenportion so as to provide a given uncapped portion.
 50. A methodaccording to claim 36 wherein the first dielectric cap deposited on thefirst given portion has a first given area, a second given area, and athird given area, the first given area having a first given height, thesecond given area having a second given height, and the third given areahaving a third given height, the first given height being lower than thesecond given height, and the second given height being lower than thethird given height, wherein the step of rapid thermal annealing of thefirst dielectric cap tunes the plurality of quantum wells beneath thefirst given area to a first tuned bandgap, the plurality of quantumwells beneath the second given area to a second tuned bandgap, and theplurality of quantum wells beneath the third given area to a third tunedbandgap, wherein the third tuned bandgap is greater than the secondtuned bandgap, and the second tuned bandgap is greater than the firsttuned bandgap.
 51. A method according to claim 50 wherein the topsurface of the single semiconductor wafer is entirely covered by thefirst given portion.
 52. A method according to claim 50 wherein the topsurface of the single semiconductor wafer is partially covered by thefirst given portion so as to provide a given uncapped portion.
 53. Amethod according to claim 52 wherein the single semiconductor wafercomprises a first section, a second section, a third section, and afourth section, the first section consisting of the plurality of quantumwells disposed beneath the given uncapped portion, the second sectionconsisting of the plurality of quantum wells disposed beneath the firstgiven region, the third section consisting of the plurality of quantumwells disposed beneath the second given region, and the fourth sectionconsisting of the plurality of quantum wells disposed beneath the thirdgiven region, wherein the first section comprises the given bandgap, thesecond section comprises the first tuned bandgap, the third sectioncomprises the second tuned bandgap, and the fourth section comprises thethird tuned bandgap.
 54. A method according to claim 53 wherein thefirst section comprises a first given photoluminescence shiftcorresponding to the given bandgap, the second section comprises asecond given photoluminescence shift corresponding to the first tunedbandgap, the third section comprises a photoluminescence shiftcorresponding to the second tuned bandgap, and the fourth sectioncomprises a fourth given photo luminescence shift corresponding to thethird tuned bandgap. 55.-67. (canceled)
 68. A method according to claim36 further comprising the step of positioning a sacrificial layer on thesingle semiconductor wafer prior to the step of depositing the firstdielectric cap on the top surface of the single semiconductor wafer. 69.A method according to claim 68 wherein the sacrificial layer is gradedfrom a first portion at a first height to a second portion at a secondheight, the first height being lower than the second height.
 70. Amethod according to claim 68 wherein the sacrificial layer is steppedfrom a first substantially flat portion to a second substantially flatportion, and further wherein the first substantially flat portion islower than the second substantially flat portion.
 71. A method accordingto claim 68 wherein the sacrificial layer on the single semiconductorwafer comprises a given portion of the single semiconductor waferdesignated as the sacrificial layer.
 72. A method according to claim 68wherein the sacrificial layer positioned on the single semiconductorwafer comprises a dielectric layer deposited thereon.
 73. A methodaccording to claim 68 wherein the sacrificial layer positioned on thesingle semiconductor layer comprises a metal layer deposited thereon.74. A method according to claim 36 further comprising the step ofdepositing a sacrificial top cladding layer on the top surface of thesingle semiconductor wafer prior to the step of depositing a firstdielectric cap.
 75. A method according to claim 74 wherein thesacrificial top cladding layer comprises a stepped top surface.
 76. Amethod according to claim 74 wherein the sacrificial top cladding layercomprises an inclined top surface.
 77. A method according to claim 74wherein the sacrificial top cladding layer is deposited by a gray scalemasking technique.
 78. A method according to claim 74 wherein thesacrificial top cladding layer is deposited by a dry etching technique.79. A method according to claim 36 further comprising a step ofproviding ion implantation to the top surface of the singlesemiconductor wafer.
 80. A method according to claim 79 wherein the ionimplantation introduces into the single semiconductor wafer at least oneselected from a group consisting of impurities and vacancies.
 81. Amethod according to claim 80 wherein the selected at least one ofimpurities and vacancies are introduced into the single semiconductor ata first given height in a first section and at a second given height ina second section.
 82. A method according to claim 81 further comprisingthe step of depositing an implantation mask on the top surface of thesingle semiconductor wafer so as to introduce the at least one ofimpurities and vacancies at the first given height and the second givenheight in the first section and the second section, respectively.
 83. Asemiconductor structure comprising: a semiconductor substrate having agiven horizontal cross-section, a first section defined in one portionof the given horizontal cross-section of the substrate, and a secondsection defined in another portion of the given horizontal cross-sectionof the substrate; a first plurality of quantum wells formed in the firstsection, the first plurality of quantum wells having a given bandgap; asecond plurality of quantum wells formed in the second section, thesecond plurality of quantum wells modified by depositing a cap on thesecond section, and rapid thermal annealing of the cap for a given timeand at a given temperature, so as to tune the second plurality ofquantum wells to a tuned bandgap; wherein the tuned bandgap is greaterthan the given bandgap.
 84. (canceled)